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19-2383; Rev 0; 4/02
1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver
General Description
The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. The MAX9320B features ultra-low propagation delay (208ps), part-to-part skew (20ps), and output-to-output skew (6ps) with 30mA maximum supply current, making this device ideal for clock distribution. For interfacing to differential PECL and LVPECL signals, this device operates over a +3.0V to +5.5V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5V supply. For differential ECL and LVECL operation, this device operates from a -3.0V to -5.5V supply. The MAX9320B is offered in industry-standard 8-pin TSSOP and SO packages.
Features
o Improved Second Source of the MC10EP11D o +3.0V to +5.5V Differential PECL/LVPECL Operation o -3.0V to -5.5V ECL/LVECL Operation o Low 22mA Supply Current o 20ps Part-to-Part Skew o 6ps Output-to-Output Skew o 208ps Propagation Delay o Minimum 300mV Output at 3GHz o Outputs Low for Open Input o ESD Protection >2kV (Human Body Model)
MAX9320B
Applications
Precision Clock Distribution Low-Jitter Data Repeater Protection Switching
PART MAX9320BESA MAX9320BEUA*
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 SO 8 TSSOP
*Future product--contact factory for availability.
Pin Configuration
D VIHD - VILD D tPLHD Q_ VOH - VOL Q tPHLD
VIHD VILD
Q0 1
VOH VOL
MAX9320B
50k 80k
8 VCC 7D 60k 6D
Q0 2 Q1 3
80% 0V (DIFFERENTIAL) (Q_) - (Q_) 20% tR
80% 0V (DIFFERENTIAL) 20% tF
100k Q1 4 5 VEE
TSSOP/SO
Figure 1. Differential Transition Time and Propagation Delay Timing Diagram ________________________________________________________________ Maxim Integrated Products 1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver MAX9320B
ABSOLUTE MAXIMUM RATINGS
VCC to VEE .............................................................................+6V D or D....................................................VEE - 0.3V to VCC + 0.3V D or D with the Other Floating............. VCC - 5.0V to VCC + 0.3V D to D .................................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Output Power Dissipation (TA = +70C) 8-Pin TSSOP (derate 4.5mW/C above +70C) .................................362mW 8-Pin SO (derate 5.9mW/C above +70C) .................................471mW Junction-to-Ambient Thermal Resistance in Still Air 8-Pin TSSOP ............................................................+221C/W 8-Pin SO...................................................................+170C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 8-Pin TSSOP ............................................................+155C/W 8-Pin SO.....................................................................+99C/W Junction-to-Case Thermal Resistance 8-Pin TSSOP ..............................................................+39C/W 8-Pin SO.....................................................................+40C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (D, D, Q_, Q_) .................................>2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
DIFFERENTIAL INPUT (D, D) High Voltage of Differential Input Low Voltage of Differential Input Differential Input Voltage Input High Current D Input Low Current D Input Low Current Single-Ended Output High Voltage VIHD VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V
VILD VIHD VILD IIH IILD IILD VCC - VEE 3.8V VCC - VEE 3.8V VCC - VEE 3.8V VCC - VEE 3.8V
VEE
VCC - 0.1 3.0 150
VEE
VCC - 0.1 3.0 150
VEE
VCC - 0.1 3.0 150
V
0.1
0.1
0.1
V A A A
-100 -140 -150 -175
+100 +140 +150 +175
-100 -140 -150 -175
+100 +140 +150 +175
-100 -140 -150 -175
+100 +140 +150 +175
DIFFERENTIAL OUTPUTS (Q_, Q__) VOH Figure 1 VCC - 1.135 VCC - 0.885 VCC - 1.07 VCC - 0.82 VCC - 1.01 VCC - 0.76 V
2
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1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER Single-Ended Output Low Voltage Differential Output Voltage POWER SUPPLY Supply Current IEE (Note 4) 20 28 22 28 23 30 mA SYMBOL CONDITIONS -40C MIN VCC - 1.935 550 TYP MAX MIN +25C TYP MAX VCC - 1.62 MIN VCC - 1.81 550 +85C TYP MAX VCC - 1.56 UNITS
MAX9320B
VOL VOH - VOL
Figure 1
VCC VCC - 1.685 - 1.87 550
V
Figure 1
mV
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V, input frequency 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5)
PARAMETER Differential Input-toOutput Delay Output-toOutput Skew Part-to-Part Skew SYMBOL tPLHD, tPHLD CONDITIONS -40C MIN 145 TYP 220 MAX 265 MIN 155 +25C TYP 208 MAX 265 MIN 160 +85C TYP 203 MAX 270 UNITS
Figure 1
ps
tSKOO
(Note 6)
6
30
6
30
6
30
ps
tSKPP
(Note 7) fIN = 1.5GHz, clock pattern (Note 8)
20 1.7 0.6
120 2.8 1.5
20 1.7 0.6
110 2.8 1.5
20 1.7 0.6
110 2.8
ps
Added Random Jitter
tRJ
fIN = 3.0GHz, clock pattern (Note 8) 3.0Gbps 223 - 1 PRBS pattern (Note 8)
ps (RMS) 1.5 ps (P-P)
Added Deterministic Jitter
tDJ
57
80
57
80
57
80
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3
1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver MAX9320B
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V, input frequency 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS VOH - VOL 300mV, clock pattern, Figure 1 fMAX VOH - VOL 550mV, clock pattern, Figure 1 -40C MIN 3.0 TYP MAX MIN 3.0 +25C TYP MAX MIN 3.0 GHz 2.0 2.0 2.0 +85C TYP MAX UNITS
Switching Frequency
Output Rise/Fall Time (20% to 80%)
tR, tF
Figure 1
50
95
120
50
98
120
50
105
120
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25C. Guaranteed by design and characterization over the full operating temperature range. Note 4: All pins open except VCC and VEE. Note 5: Guaranteed by design and characterization. Limits are set at 6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 8: Device jitter added to the input signal.
Typical Operating Characteristics
(VCC = 5V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT, IEE vs. TEMPERATURE
24 23 SUPPLY CURRENT (mA) 22 21 20 19 18 17 16 15 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX9320B toc01
OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY
0.7 OUTPUT AMPLITUDE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 500 1000 1500 2000 2500 3000 3500 FREQUENCY (MHz) 85 80
MAX9320B toc02
TRANSITION TIME vs. TEMPERATURE
MAX9320B toc03
25
0.8
110 105 TRANSITION TIME (ps) 100 95 90 tF
tR
-40
-15
10
35
60
85
TEMPERATURE (C)
4
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1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver
Typical Operating Characteristics (continued)
(VCC = 5V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD
VIHD - VILD = 0.5V 215 PROPAGATION DELAY (ps) 210 205 200 195 190 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 VIHD (V) tPHLD tPLHD
MAX9320B toc04
MAX9320B
PROPAGATION DELAY vs. TEMPERATURE
230 PROPAGATION DELAY (ps) 220 210 200 190 180 170 160 -40 -15 10 35 60 85 TEMPERATURE (C) tPHLD
MAX9320B toc05
220
240 tPLHD
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME Q0 Q0 Q1 Q1 VEE D D VCC FUNCTION Noninverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Negative Supply Voltage Inverting Differential Input. 50k pullup to VCC and 100k pulldown to VEE. Noninverting Differential Input. 80k pullup to VCC and 60k pulldown to VEE. Positive Supply Voltage. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.
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5
1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver MAX9320B
Detailed Description
The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. For interfacing to differential PECL and LVPECL signals, this device operates over a +3.0V to +5.5V supply range, allowing high-performance clock and data distribution in systems with a nominal 3.3V or 5V supply. For differential ECL and LVECL operation, this device operates from a -3.0V to -5.5V supply.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F value capacitor closest to the device. Use multiple parallel ground vias for low inductance.
Traces
Input and output trace characteristics affect the performance of the MAX9320B. Connect each signal of a differential input or output to a 50 characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces.
Inputs
The maximum magnitude of the differential input from D to D is 3.0V. This limit also applies to the difference between any reference voltage input and a singleended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting input, D, is biased with a 50k pullup to VCC and a 100k pulldown to VEE. The noninverting input, D, is biased with an 80k pullup to VCC and a 60k pulldown to VEE. Specifications for the high and low voltages of the differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD).
Output Termination
Terminate outputs through 50 to VCC - 2V or use an equivalent Thevenin termination. Terminate both outputs and use the same termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0.
Outputs
Output levels are referenced to VCC and are considered PECL/LVPECL or ECL/LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are PECL/LVPECL. The outputs are ECL/LVECL when VCC is connected to GND and VEE is connected to a negative supply. A differential input of at least 100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table.
Chip Information
TRANSISTOR COUNT: 182
6
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1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
9LUCSP, 3x3.EPS
MAX9320B
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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